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Verification by Error Modeling Using Testing Techniques in Hardware Verification

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Hardcover NOT from a library hand inspected by me(greg)
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Objectstaat
Heel goed
Een boek dat er niet als nieuw uitziet en is gelezen, maar zich in uitstekende staat bevindt. De kaft is niet zichtbaar beschadigd en het eventuele stofomslag zit nog om de harde kaft heen. Er ontbreken geen bladzijden en er zijn geen bladzijden beschadigd. Er is geen tekst onderstreept of gemarkeerd en er is niet in de kantlijn geschreven. Er kunnen zeer minimale identificatiemerken aan de binnenzijde van de kaft zijn aangebracht. De slijtage is zeer minimaal. Bekijk de aanbieding van de verkoper voor de volledige details en een beschrijving van gebreken. Alle staatdefinities bekijkenwordt in nieuw venster of op nieuw tabblad geopend
Opmerkingen van verkoper
“Hardcover NOT from a library hand inspected by me(greg)”
ISBN
9781402076527
Subject Area
Computers, Technology & Engineering
Publication Name
Verification by Error Modeling : Using Testing Techniques in Hardware Verification
Item Length
9.3 in
Publisher
Springer
Subject
Software Development & Engineering / Quality Assurance & Testing, Cad-Cam, Electronics / Circuits / Vlsi & Ulsi, Electronics / Circuits / Integrated, Electronics / Circuits / General, Electrical
Publication Year
2003
Series
Frontiers in Electronic Testing Ser.
Type
Textbook
Format
Hardcover
Language
English
Author
Zeljko Zilic, Katarzyna Radecka
Item Width
6.1 in
Item Weight
39.5 Oz
Number of Pages
Xv, 216 Pages

Over dit product

Product Information

1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be "imminently doable" by Intel fellow J. Crawford at Microprocessor Forum in October 2002 40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.

Product Identifiers

Publisher
Springer
ISBN-10
1402076525
ISBN-13
9781402076527
eBay Product ID (ePID)
5978587

Product Key Features

Author
Zeljko Zilic, Katarzyna Radecka
Publication Name
Verification by Error Modeling : Using Testing Techniques in Hardware Verification
Format
Hardcover
Language
English
Subject
Software Development & Engineering / Quality Assurance & Testing, Cad-Cam, Electronics / Circuits / Vlsi & Ulsi, Electronics / Circuits / Integrated, Electronics / Circuits / General, Electrical
Publication Year
2003
Series
Frontiers in Electronic Testing Ser.
Type
Textbook
Subject Area
Computers, Technology & Engineering
Number of Pages
Xv, 216 Pages

Dimensions

Item Length
9.3 in
Item Width
6.1 in
Item Weight
39.5 Oz

Additional Product Features

LCCN
2003-062044
Intended Audience
Scholarly & Professional
Series Volume Number
25
Number of Volumes
1 Vol.
Lc Classification Number
Tj212-225
Reviews
From the reviews: "This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. ... The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004), From the reviews:"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. … The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004), From the reviews: "This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. … The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)
Table of Content
Boolean Function Representations.- Don't Cares and Their Calculation.- Testing.- Design Error Models.- Design Verification by At.- Identifying Redundant Gate and Wire Replacements.- Conclusions and Future Work.
Copyright Date
2003
Dewey Decimal
621.39/5
Dewey Edition
22
Illustrated
Yes
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