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SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hard
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Specificaties
- Objectstaat
- ISBN-13
- 9780387333991
- Book Title
- SystemVerilog for Design Second Edition
- ISBN
- 9780387333991
Over dit product
Product Identifiers
Publisher
Springer
ISBN-10
0387333991
ISBN-13
9780387333991
eBay Product ID (ePID)
52762948
Product Key Features
Number of Pages
Xxx, 418 Pages
Language
English
Publication Name
Systemverilog for Design : a Guide to Using Systemverilog for Hardware Design and Modeling
Publication Year
2006
Subject
Computer Simulation, Hardware / General, Cad-Cam, Electronics / Circuits / General, Electronics / Digital, Logic Design
Features
Revised
Type
Textbook
Subject Area
Computers, Technology & Engineering
Format
Hardcover
Dimensions
Item Height
0.4 in
Item Weight
62.8 Oz
Item Length
9.3 in
Item Width
6.1 in
Additional Product Features
Edition Number
2
Intended Audience
Scholarly & Professional
LCCN
2006-928944
Dewey Edition
22
Number of Volumes
1 vol.
Illustrated
Yes
Dewey Decimal
621.392
Edition Description
Revised edition
Table Of Content
to SystemVerilog.- SystemVerilog Declaration Spaces.- SystemVerilog Literal Values and Built-in Data Types.- SystemVerilog User-Defined and Enumerated Types.- SystemVerilog Arrays, Structures and Unions.- SystemVerilog Procedural Blocks, Tasks and Functions.- SystemVerilog Procedural Statements.- Modeling Finite State Machines with SystemVerilog.- SystemVerilog Design Hierarchy.- SystemVerilog Interfaces.- A Complete Design Modeled with SystemVerilog.- Behavioral and Transaction Level Modeling.
Synopsis
SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs.The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis.SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language.In addition, the second edition features a new chapter that explanis the SystemVerilog "packages," a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools., SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis. SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language. In addition, the second edition features a new chapter that explanis the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools., In its updated second edition, this book has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes adopted between the first edition of the book and the finalization of the new standard. The book accurately reflects the syntax and semantic changes to the SystemVerilog language, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter that explains the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools., In its updated second edition, this book has been rewritten chapter-by-chapter to accurately reflect the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information
LC Classification Number
TK7867-7867.5
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